The present invention relates to jitter attenuators.
Jitter attenuators are used to compensate for phase variations in an input signal. Uncompensated jitter can be a significant source of error. In transmission systems such as T3 and E3, the clock is encoded with the data. A receiver will extract the clock from the coded datastream and provide the extracted clock and data itself This clock can then be used to retransmit the data to the next node. Jitter is obviously undesirable since any phase variation of the clock can be passed along from node to node.
There are many causes of jitter. For example, the transmission media may transmit higher frequency portions of the signal faster than lower frequency portions.
Typically, the received clock is filtered and smoothed to remove the jitter. An elastic buffer, such as a FIFO, is sometimes used to buffer the difference in rates of the received jittery clock and the retransmitted data. See, for example, U.S. Pat. No. 5,090,025.
Another example of a jitter attenuator is shown in U.S. Pat. No. 5,493,243. This patent shows using an up/down counter and a subsequent decoder to control the digital frequency synthesizer. The input clock is used to decrement the counter, while the output, divided-down clock is used to increment the counter. Each change in the count causes a change in the phase of the synthesized frequency.
It would be desirable to have a digital jitter attenuator which corrects for jitter, but which corrects slowly enough to avoid tracking phase variations which are transient.